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MoBL(R),CY62126EV30
1-Mbit (64K x 16) Static RAM
Features

Functional Description
The CY62126EV30 is a high performance CMOS static RAM organized as 64K words by 16 bits[1]. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device in standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when:

High speed: 45 ns Temperature ranges Industrial: -40C to +85C Automotive: -40C to +125C Wide voltage range: 2.2V to 3.6V Pin compatible with CY62126DV30 Ultra low standby power Typical standby current: 1 A Maximum standby current: 4 A Ultra low active power Typical active current: 1.3 mA at f = 1 MHz Easy memory expansion with CE and OE features Automatic power down when deselected CMOS for optimum speed and power Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II packages

Deselected (CE HIGH) Outputs are disabled (OE HIGH) Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) Write operation is active (CE LOW and WE LOW)

To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A15). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the "Truth Table" on page 9 for a complete description of read and write modes.
Logic Block Diagram
Note 1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation Document #: 38-05486 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 5, 2009
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Pin Configurations
Figure 1. 44-Ball VFBGA (Top View) Figure 2. 44-Pin TSOP II (Top View)[2]
Table 1. Product Portfolio Power Dissipation Product Range Min CY62126EV30LL Industrial CY62126EV30LL Automotive 2.2 2.2 VCC Range (V) Typ[3] 3.0 3.0 Max 3.6 3.6 45 55 Speed (ns) Operating, ICC (mA) f = 1 MHz Typ[3] 1.3 1.3 Max 2 4 f = fmax Typ[3] 11 11 Max 16 35 Standby, ISB2 (A) Typ[3] 1 1 Max 4 30
Notes 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
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Maximum Ratings
Exceeding maximum ratings may shorten the battery life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage to Ground Potential................................. -0.3V to 3.6V (VCCmax + 0.3V) DC Voltage Applied to Outputs in High-Z State[4, 5] ................ -0.3V to 3.6V (VCCmax + 0.3V) DC Input Voltage[4, 5] ...............-0.3V to 3.6V (VCCmax + 0.3V) Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current.................................................... > 200 mA
Operating Range
Device CY62126EV30LL Range Industrial Ambient Temperature -40C to +85C VCC[6] 2.2V to 3.6V
Automotive -40C to +125C
Electrical Characteristics (Over the Operating Range)
Parameter VOH VOL VIH VIL IIX IOZ ICC Description Test Conditions 45 ns (Industrial) Min 2.0 2.4 0.4 0.4 1.8 2.2 -0.3 -0.3 -1 -1 11 1.3 1 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 16 2.0 4 1.8 2.2 -0.3 -0.3 -4 -4 11 1.3 1 Typ[1] Max 55 ns (Automotive) Min 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +4 +4 35 4.0 35 A Typ[1] Max Unit V V V V V V V V A A mA
Output HIGH Voltage IOH = -0.1 mA IOH = -1.0 mA, VCC > 2.70V Output LOW Voltage Input HIGH Voltage Input LOW Voltage IOL = 0.1 mA IOL = 2.1mA, VCC > 2.70V VCC = 2.2V to 2.7V VCC = 2.7V to 3.6V VCC = 2.2V to 2.7V VCC = 2.7V to 3.6V GND < VO < VCC, Output Disabled VCC = VCCmax IOUT = 0 mA CMOS levels
Input Leakage Current GND < VI < VCC Output Leakage Current
VCC Operating Supply f = fmax = 1/tRC Current f = 1 MHz Automatic CE Power down Current --CMOS Inputs
ISB1
CE > VCC - 0.2V, VIN > VCC - 0.2V, VIN < 0.2V) f = fmax (Address and Data Only), f = 0 (OE, BHE, BLE and WE), VCC = 3.60V CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V
ISB2 [7]
Automatic CE Power down Current --CMOS Inputs
1
4
1
30
A
Capacitance
For all packages. Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Notes 4. VIL(min) = -2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 6. Full device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after Vcc stabilization. 7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
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Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Figure 3. AC Test Loads and Waveforms VCC OUTPUT R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, two-layer printed circuit board VFBGA Package 58.85 17.01 TSOP II Package 28.2 3.4 Unit C/W C/W
Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH 2.2V - 2.7V 16600 15400 8000 1.2 2.7V - 3.6V 1103 1554 645 1.75 Unit Ohms Ohms Ohms Volts
Parameters R1 R2 RTH VTH
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR[7] tCDR tR[9]
[8]
Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Conditions VCC= VDR, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Industrial Automotive
Min 1.5
Typ[1]
Max 3 30
Unit V A A ns ns
0 tRC Figure 4. Data Retention Waveform VCC(min)
tCDR DATA RETENTION MODE VDR > 1.5V
VCC CE
VCC(min)
tR
Notes 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s.
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Switching Characteristics
Over the Operating Range [10, 11] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle [14] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BHE / BLE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z
[12, 13] [12]
Description
45 ns (Industrial) Min 45 45 10 45 22 5 18 10 18 0 45 22 5 18 45 35 35 0 0 35 35 25 0 18 10
[12] [12, 13]
55 ns (Automotive) Min 55 55 10 55 25 5 20 10 20 0 55 25 5 20 55 40 40 0 0 40 40 25 0 20 10 Max
Max
Unit
Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z
[12]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High Z [12, 13] CE LOW to Low Z [12] CE HIGH to High Z
[12, 13]
CE LOW to Power Up CE HIGH to Power Down BHE / BLE LOW to Data Valid BHE / BLE LOW to Low Z BHE / BLE HIGH to High Z
Notes 10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance. 11. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 12. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 13. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 14. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
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Switching Waveforms
Figure 5. Read Cycle No. 1(Address transition controlled)[15, 16]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 6. Read Cycle No. 2 (OE controlled)[16, 17]
ADDRESS
tRC CE tACE OE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB DATA VALID HIGH IMPEDANCE tHZOE tPD tHZCE
Notes 15. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 16. WE is HIGH for read cycle. 17. Address valid before or similar to CE and BHE, BLE transition LOW.
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Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE controlled)[14, 18, 19]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
BHE/BLE
tBW
OE DATA IO NOTE 20 tHZOE
tSD DATAIN
tHD
Figure 8. Write Cycle No. 2 (CE controlled)[14, 18, 19]
tWC ADDRESS tSCE CE
tSA
WE
tAW tPWE
tHA
BHE/BLE
tBW
OE tSD DATA IO NOTE 20 tHZOE DATAIN tHD
Notes 18. Data IO is high impedance if OE = VIH. 19. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 20. During this period, the IOs are in output state. Do not apply input signals.
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Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE controlled, OE LOW [19]
tWC ADDRESS tSCE CE
BHE/BLE tAW WE tSA
tBW tHA tPWE
tSD DATA IO NOTE 20 tHZWE DATAIN
tHD
tLZWE
Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW)[19]
tWC ADDRESS
CE tSCE
tAW BHE/BLE tSA WE
tHZWE
tHA tBW
tPWE tSD DATAIN
tLZWE
tHD
DATA IO
NOTE 20
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Truth Table
CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High Z High Z Data Out (IO0-IO15) Data Out (IO0-IO7); IO8-IO15 in High Z Data Out (IO8-IO15); IO0-IO7 in High Z High Z High Z High Z Data In (IO0-IO15) Data In (IO0-IO7); IO8-IO15 in High Z Data In (IO8-IO15); IO0-IO7 in High Z Mode Deselect/Power Down Output Disabled Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 45 55 Ordering Code CY62126EV30LL-45BVXI CY62126EV30LL-45ZSXI CY62126EV30LL-55BVXE CY62126EV30LL-55ZSXE Package Diagram Package Type Operating Range Industrial Automotive 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) 51-85087 44-pin Thin Small Outline Package II (Pb-free) 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) 51-85087 44-pin Thin Small Outline Package II (Pb-free)
Contact your local Cypress sales representative for availability of other parts.
Document #: 38-05486 Rev. *E
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Package Diagrams
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm) (51-85150)
TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C 1.00 MAX
SEATING PLANE 0.26 MAX. C
51-85150-*D
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Package Diagrams (continued)
Figure 12. 44-Pin TSOP II (51-85087)
51-85087-*A
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Document History Page
Document Title: MoBL(R) CY62126EV30, 1-Mbit (64K x 16) Static RAM Document Number: 38-05486 Rev. ** *A ECN No. 202760 300835 Submission Date See ECN See ECN Orig. of Change AJU SYT New data sheet Converted from Advance Information to Preliminary Specified Typical standby power in the Features Section Changed E3 ball from DNU to NC in the Pin Configuration for the FBGA Package and removed the footnote associated with it on page #2 Changed tOHA from 6 ns to 10 ns for both 35- and 45-ns speed bins, respectively Changed tDOE, tSD from 15 to 18 ns for 35-ns speed bin Changed tHZOE, tHZBE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35- and 45-ns speed bins, respectively Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35- and 45-ns speed bins, respectively Changed tSCE,tBW from 25 and 40 ns to 30 and 35 ns for the 35- and 45-ns speed bins, respectively Changed tAW from 25 to 30 ns and 40 to 35 ns for 35 and 45-ns speed bins respectively Changed tDBE from 35 and 45 ns to 18 and 22 ns for the 35 and 45 ns speed bins respectively Removed footnote that read "BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE" on page # 4 Removed footnote that read "If both BHE and BLE are toggled together, then tLZBE is 10 ns" on page # 5 Added Pb-free package information Converted from Preliminary to Final Removed 35 ns Speed Bin Removed "L" version of CY62126EV30 Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for f = fmax Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz Changed ISB1, ISB2 (max) from 1 A to 4 A Changed ISB1, ISB2 (Typ) from 0.5 A to 1 A Changed ICCDR (max) from 1.5 A to 3 A Changed the AC Test load Capacitance value from 50 pF to 30 pF Changed tLZOE from 3 to 5 ns Changed tLZCE from 6 to 10 ns Changed tHZCE from 22 to 18 ns Changed tLZBE from 6 to 5 ns Changed tPWE from 30 to 35 ns Changed tSD from 22 to 25 ns Changed tLZWE from 6 to 10 ns Updated the Ordering Information table. Added footnote #7 related to ISB2 and ICCDR Added footnote #11 related AC timing parameters Added Automotive information Updated Ordering Information table Description of Change
*B
461631
See ECN
NXR
*C *D *E
925501 1045260 2631771
See ECN See ECN 01/07/09
VKN VKN
NXR/PYRS Changed CE condition from X to L in Truth table for Output Disable mode Updated template
Document #: 38-05486 Rev. *E
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
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(c) Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05486 Rev. *E
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
Revised January 5, 2009
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